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ing an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to
enable the master to generate the STOP condition.
- Figure 19 on page 9 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of
data transfer are possible:
- Master Transmitter to Slave Receiver . The first byte transmitted by the master is the slave address, followed by a number of data bytes.
The slave returns an acknowledge bit after the slave address and each received byte.
- Slave Transmitter to Master Receiver . The first byte, the slave address, is transmitted by the master. The slave then returns an acknowl-
edge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the
serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since
a repeated START condition is also the beginning of the next serial transfer, the bus will not be released.
The AS1115 can operate in the following slave modes:
- Slave Receiver Mode . Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is trans-
mitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction bit.
- Slave Transmitter Mode . The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode
the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the AS1115 while the serial clock
is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.
I2C Device Address Byte
The address byte (see Figure 20) is the first byte received following the START condition from the master device.
Figure 20. I2C Device Address Byte
MSB
6
5
4
3
2
1
LSB
predefined address:
updated address:
0
MSB
0
0
6
0
0
5
0
0
4
0
0
3
0
0
2
A1
0
1
A0
R/W
LSB
R/W
- The default slave address is factory-set to 0000000.
- The two LSB bits of the address byte are the device select bits, A0 to A1, which can be set by the self address command after startup. A
maximum of four devices with the same pre-set code can therefore be connected on the same bus at one time.
A short writes a logical “0” whereas an open writes a logical “1” as address bit ( see Figure 26 on page 15 ).
- The last bit of the address byte (R/W) define the operation to be performed. When set to a 1 a read operation is selected; when set to a 0
a write operation is selected.
Following the START condition, the AS1115 monitors the I2C bus, checking the device type identifier being transmitted. Upon receiving the
address code, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.
I2C Device Self Addressing
If this feature is used, 2 of the 16 key readback nodes can be left open or shorted for self-addressing. This is done with KEYA together with
SEGG (A0) and SEGF (A1). This two nodes cannot be used for key-readback in this case. After startup all devices have the predefined address
0000000. A single command for self addressing will update all connected AS1115. This command has to be done after startup or every time the
AS1115 gets disconnected from the supply. The I2C address definition must be done with fixed connection, since I2C detection is excluded from
debounce time of key registers.
Revision 1.08
10 - 25
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